发明名称 Wiring layout for bipolar and unipolar insulated gate transistors.
摘要 A semiconductor device comprises a drain region, base regions, gate electrodes formed over the drain region between two adjacent base regions through an insulating layer such that each bridges the surface of the drain region to partially cover the two adjacent base regions, source regions provided in the base regions, a source electrode provided on the source regions, and a metal gate electrode wiring contacting the gate electrodes. The metal gate electrode wiring includes closed loop portions and the source electrode is divided into branch sections, each corresponding to the closed loop portion.
申请公布号 EP0237932(A2) 申请公布日期 1987.09.23
申请号 EP19870103475 申请日期 1987.03.11
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 KUWAHARA, MASASHI C/O PATENT DIVISION,
分类号 H01L29/68;H01L23/528;H01L29/06;H01L29/417;H01L29/423;H01L29/739;H01L29/78 主分类号 H01L29/68
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