| 摘要 |
PURPOSE:To improve the reliability of information of a DRAM by forming the same conductivity type semiconductor region as a semiconductor substrate in contact with a semiconductor region of source or drain in the lower portions of MISFET and capacity element of a memory cell to prevent minority carrier from invading to the semiconductor region. CONSTITUTION:A p-type semiconductor region 12 is formed similarly in pattern to the surface of a substrate exposed from a gate electrode 6, a field insulating film 2, and an insulating film 10 of the side of a capacity electrode 9. The region 12 under an n<+> type semiconductor region 4 of MISFET and a p-type semiconductor region 11 of a capacity element are not separated therebetween. In other words, the region 11 and the region 12 are substantially integrated. Thus, minority carrier jumped by the region 11 under the capacity element does not invade into the region 4 of source, drain region. |
