| 摘要 |
PURPOSE:To execute both transfer and comparison in parallel by providing the titled device with two readable/writable memories, a comparator and two flag registers holding the decided result of the comparator. CONSTITUTION:At the time repeating transferring and comparing operation four times in each cycle of an input mode, the decided result of the whole of two array elements stored in the memories 3, 4 is held in the 1st flag register 6 as the flag information. At the storage of the flag information, the cycle is ended and the flag information stored in the 1st flag register 6, is transferred and stored to/in the 2nd flag register 7 and ''0'' is written in the register 6 to initialize the register 6. When the input mode cycles T0-T5 are executed, 6 array elements are stored in th memories 3, 4 of units U0-U2 while being to transfer operation equivalent to the comparison and replacement in parallel. |
