| 摘要 |
PURPOSE:To absorb a phase shift between a frame decomposed clock and a timing clock by resetting a frequency divider which generates the timing clock with a frame control signal. CONSTITUTION:Data received from a line 3 is converted by SPC 206 into parallel data. It is latched in a latch 210 with the timing clock TCK and outputted to a data bus 23. Channel data generated by an address counter 208, on the other hand, is latched in a latch 211 with the timing clock TCK and outputted to an address bus 22. A frequency divider 205, on the other hand, divides the frequency of a bit synchronizing clock phi of frequency (f) outputted from a phase-locked loop 204 to generate the clock TCK, but reset with the output signal of a NAND gate 213 when the frame control signal F is received. The frequency divider 205 is reset at the end of frame synchronization every time the frame control signal F is inputted, i.e. at intervals of one frame.
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