| 摘要 |
<p>PURPOSE:To reduce power consumption by providing a latch circuit temporarily holding an output signal in the state where the 2nd switch is turned on based on a clock signal and connecting the 1st and 2nd switches to the 2nd signal line. CONSTITUTION:When address signals AD1-ADF change to cause the clock signal phi at a level H, MOSQA1-MOSQAM and QB1-QBN are turned on. When the clock signal phi comes to a level L after a certain period, the MOSQA 1-MOSQAM and the QB1-QBN are turned off, and a current does not flow to loads MOSQL1-MOSQLM and QPL-PQN. When the clock signal phi comes to a level L, reading action is not prevented, because data is held while a memory circuit 14 is reading data on bit lines O1-ON at a level H. Thus a power source current flows only when the address signal changes, and does not flow in other cases, whereby power consumption can be substantially reduced.</p> |
