| 摘要 |
<p>PURPOSE:To lower power consumption for writing by providing plural memory cells, a means for selecting the memory cell corresponding to the address infor mation and a means for supplying a writing current to the selected memory cell through an field effect transistor. CONSTITUTION:A transistor Q3 is driven by a writing signal W' having a voltage substantially equal to a potential difference between a writing potential VPP and a selecting potential of a memory cell during a reading operation as an amplitude level. Thus, a P channel transistor Q5 and an N channel transistor Q4 are connected in series between terminals 3, 4 and a gate 3-3 of the transistor Q3 is connected to their connecting point. A writing control signal WC corresponding to the input data is commonly supplied to the gates of the transistors Q4, Q5, and to the terminal 4, a voltage having a potential level VCC is supplied and the potential level VCC is substantially equal to a selecting level of the memory cell transistor. Thereby, the writing power is supplied to the memory cell transistor Q1 through the transistor Q3 to perform the writing.</p> |
