| 摘要 |
PURPOSE:To reduce parasitic resistance sufficiently, by using a wafer wherein the width of a forbidden band in a part of a third semiconductor layer wherein this layer contacts with a second semiconductor layer is larger than that of the second semiconductor layer. CONSTITUTION:First, an N<+> type GaAs layer 12 as a first semiconductor layer to be a collector, and subsequently an N-type GaAs layer 13, are made to grow epitaxially on a half-insulative GaAs substrate 11. Subsequently, a P<+> type GaAs layer 14 is made to grow epitaxially as a second semiconductor layer to be a base and further an N-type AlGaAs layer 15 and an N<+> type GaAs layer 16 are made to grow epitaxially as a third semiconductor layer to be an emitter. Next, the AlGaAs layer 15 is exposed. Then, a high-resistance layer 19 is formed by ion implantation and annealing. Thereafter a photoresist pattern having an opening in a base electrode forming region is formed, and the AlGaAs layer is etched to form a concavity expanding from a part of an external base region to a part of the resistance layer 19, and a base electrode 18 is formed therein. Then, an emitter electrode 21 and a collector electrode 22 are formed.
|
