发明名称 TROUBLE PROCESSING SYSTEM FOR MICROPROGRAM CONTROL DEVICE
摘要 PURPOSE:To correct an error in case of one bit trouble regardless of an intermittent trouble or a fixed trouble and to separate and cut a block of a control memory corresponding only in case of several bit troubles by providing an error detecting/correcting circuit. CONSTITUTION:The error detecting/correcting circuit 10 checks whether or not the contents of the output data bitted at control memories 7a and 7b are normal, and corrects the bit error regardless of the intermittent trouble or the fixed trouble when one bit error exists. When the trouble is several bit ones, based upon the output of the trouble address and an address comparator 6a detected by the circuit 10, the trouble generating sub-compartment is divided and the access to a sub-compartment 7-2 is prevented. Namely, the logical address of the microinstruction is modified through a degrade register 1, an address modifying circuit 2a and an address register 3a, to be modified and the access to the sub-compartment 7-2 is prevented. Thus, the block of the corresponding control memory can be separated and cut.
申请公布号 JPS61269755(A) 申请公布日期 1986.11.29
申请号 JP19850110552 申请日期 1985.05.24
申请人 NEC CORP 发明人 KATSUTA NOBUO;ITO YUKIO
分类号 G06F9/22;G06F12/16 主分类号 G06F9/22
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