GENERATOR FOR MEMORY CONTROL SIGNAL

摘要

PURPOSE:To form easily a picture memory by attaining a high-speed operation of a DRAM for storage of video signals. CONSTITUTION:The 1st shift register consists of a D-ff 1 and a D-FF 2; while the 2nd shift register consists of a D-FF 3 and a D-FF 4 respectively. The clocks of the 1st and 2nd shift registers are referred to as CLK and the inver sion of CLK respectively. Furthermore, the input of the 2nd shift register is equal to the 1st bit output, the inversion of Q1 of the 1st shift register. Then the 1st shift register defines 4fsc as a clock and uses the signal obtained by giving 1/4 division to 4fsc as an input. While the 2nd shift register defines the signal obtained by inverting 4fsc as a clock and uses the output of the 1st shift register as an input. Then a logical operation is performed between the outputs of the 1st and 2nd shift registers for production of such memory control signals as the inversions of RAS and CAS, and WE, etc.