| 摘要 |
PURPOSE:To obtain a memory device having a small occupying area and large capacitances by laminating a first insulating film and an electrode and a second insulating film and an electrode in a groove formed to an Si substrate in succession and connecting two capacitances in parallel. CONSTITUTION:An opening is bored to an oxide film 3 on the surface of an insulated isolated Si substrate and a groove 5 is shaped through RIE, and the surface is coated with PSG 22 and an N layer 6 is formed through thermal diffusion. The films 22 and 3 are removed through etching and the surface is coated with an oxide film 7, and As ions are implanted 9 through a resist mask 8 to shape an N layer 10. The surface is coated with doped poly Si 11, an air gap is left in the groove 5, a resist mask 12 is applied, the film 11 is patterned and the surface is coated with an oxide film 13. An opening 15 is bored to the films 13 and 7 by a resist mask 14. Second poly Si 16 is superposed selectively to fill the groove, and a novel gate oxide film 17 is shaped. A memory device using a Nch Si gate FET is completed in accordance with a normal method. According to the constitution, when groove width and the film thickness of a capacitance electrode are selected, a large number of capacitances can be shaped by parallel connection, thus ensuring a large capacitance value, then acquiring the memory device having a small area. |
