| 摘要 |
PURPOSE:To attain ease of circuit integration by combining two FF circuits and three gate circuits so as to form a phase comparator circuit thereby eliminating the need for a time constant circuit. CONSTITUTION:An output of an FF13 to which an input signal is fed is applied to an FF14. The input to the FFs13, 14 is latched by a clock signal fed to its clock terminal 12 at the same time. Then an output of the FF13 and the input signal are added by an EOR circuit 15 and outputs of the FFs13, 14 are added by an EOR circuit 16. Further, the output of the EOR circuit 16 and signal obtained by inverting the clock signal at an inverter 18 are processed logically at an AND circuit 17. Then a phase error signal between the input signal and the clock signal is obtained between the outputs of the EOR circuit 15 and the AND circuit 17. In forming the phase comparator circuit in this way, no time constant circuit is required and then ease of circuit integration is attained. |
