发明名称 WIRING-LAYER FORMING METHOD FOR MULTILAYER WIRING STRUCTURE
摘要 PURPOSE:To prevent the yield of cracks at the step part of an interlayer insulating film, by providing a round part at the end part of a patterned wiring layer by the combination of isotropic etching and anisotropic etching. CONSTITUTION:On a semiconductor substrate 1, an insulating film 2, a first wiring layer 3 and a patterned etching mask 6 are sequentially laminated. Isotropic etching is performed by wet etching. The etching is stopped before the layer 3 is separated and patterned. After the mask 6 is removed, anisotropic etching is carried out by dry etching until the layer 3 is complately separated and patterned. After the patterned layer 3 is formed in this way, an insulating layer 4 is formed on the entire surface of the element.
申请公布号 JPS60169153(A) 申请公布日期 1985.09.02
申请号 JP19840023793 申请日期 1984.02.10
申请人 SUMITOMO DENKI KOGYO KK 发明人 IDA JIROU;HORI MINORU
分类号 H01L21/3213;(IPC1-7):H01L21/88 主分类号 H01L21/3213
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