| 摘要 |
Disclosed is a main storage failure address control system in a data processing system which comprises a plurality of main storage units (MSU) including a hardware prefix area, a main storage control unit (MCU), a plurality of data processing units (CPU), and at least one data transfer apparatus, in which when a failure occurs at the read or write operation in the main storage unit, the failed main storage address is held in a failed main storage address register FSAR (41), and the address is then stored in the hardware prefix area; wherein the failed main storage address register FSAR (41) is located in the main storage control unit. In this system, the circuit constitution for reading the failed main storage address during access to the main storage unit and for storing the address into the hardware prefix area is simplified. Thus, increasing the efficiency of the processing of the system. |
