| 摘要 |
PURPOSE:To attain the microprogram control with high efficiency by having a high-speed control memory and a low-speed control memory and switching them with each other. CONSTITUTION:For the first execution, an access is fed from a high-speed control memory HCS1 to control a microinstruction. Then a next address designating part 41 shows a low-speed control memory LCS2. Under such conditions, a next address control part NAC5 supplies an access to the LCS2 with its address and at the same time sends the address to a generating circuit NOPG7 for non- operation microinstruction NOP. The contents of the LCS2 are read at the first time after two machine cycles, and a space of a cycle is produced between both microinstructions HCS1 and LCS2. In order to prevent the space, an NOP instruction is produced by the NOPG7 and a gate circuit G is controlled by a control memory data register set control part CSDRSC8. Then the NOP instruction is selected and set to a control memory register 4, and the NOP instruction is executed in an idle cycle.
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