Manchester decoder clock multiplier

摘要

The circuit comprises a differentiator, two nonretriggerable-gated-monostable-multivibrators, a clock decoder, a data flip-flop unit, and a multiphase and frequency logic circuit. The differentiator checks the incoming Manchester encoded signal and divides it into two trigger signals one with data associated with logic "0" transitions within the Manchester signal and the second trigger signal containing data associated with logic "1" transitions within the Manchester data. One trigger signal is fed to one of the nonretriggerable-gated-monostable-multivibrator and the other trigger signal is transmitted to the second similar unit. Within these monostable multivibrator units the signals are gated and delayed by a tapped delay line which outputs a plurality of delayed signals which have waveforms built upon the occurrence of transitions within the Manchester signal associated with the logic "0" and logic "1" occurrences. Also within the monostable multivibrator, a set/reset latch is utilized to create appropriate signals to aid the control gates in blocking out undesired portions of the input trigger signals from the differentiator. The outputs of the set/reset latches are then fed to a clock decoder and onto a data flip-flop unit which is used to retrieve the data signals from the Manchester encoded signal. Outputs from the tapped delay lines within each monostable multivibrator which emit a plurality of delayed signals are fed to a multiphase and frequency logic unit which combines these delayed signals in predetermined manners to create a multiplicity of clock signals differing in frequency and phase.