| 摘要 |
PURPOSE:To reduce the scale of an interpolation circuit by using a 1-bit adder to perform interpolation after applying the serial conversion to all data. CONSTITUTION:The input data (a) of a word and 16 bits having a separated error flag EF is supplied to a shift register 1 containing a synchronizing load of 16 bits. Then the register 1 converts the data (a) into the serial data through the LSB side. At the same time, the flag EF corresponding to the data (a) of a word is latched by a 1-bit latch circuit 10. In case the data (a) has no flag EF, the data (a) is sent to a 34-bit shift register 3 in the next timing. In this case, ''0'' is added by a bit as a dummy data by the 17th clock pulse. While if the flag EF is attached to the data (a), the EF held by the circuit 10 for a time interval of a word. Thus a 1-bit multiplexer 2 selects the output of the register 3. |
