| 摘要 |
PURPOSE:To omit an error correcting circuit and a redundant bit for error correction by dividing a control memory into plural blocks and inhibiting the use of a control memory in which a fault is generated in each block. CONSTITUTION:A circuit for processing a fault is constituted by a degrading register 1, address modifying circuits 2, 2', modified address registers 3, 3', and AND circuits 10, 10'. The degrading register 1 holds the usable and inhibiting status of subcompartments in control memories 7, 7'. Namely, the degrading register 1 has the same number of bits as the subcompartments of the control memories 7, 7' and each bit corresponds to one subcompartment. The bits ''0'' and ''1'' indicate inhibiting status and usable status respectively. The address modifying circuits 2, 2' interrupt access to the subcompartment of which use is inhibited and the modified address registers 3, 3' hold modified addresses. |
