| 摘要 |
PURPOSE:To decode instruction or data without degrading a processing speed by reading out an instruction word or data to be executed next from a memory at the time when the format decoding of the instruction which is currently processed is performed. CONSTITUTION:A register selection signal as the output of an operating circuit 7 selects a register 3 when a nonbranching instruction is executed and when branching is not performed as the operation result of a conditional branching instruction, and this register selection signal selects a register, where an instruction word or data in a branch destination address is held, from registers 4-5 when the branch destination address is determined as the operation result of a conditional branching instruction. When the instruction is inputted to a format decoder circuit 6, the circuit 6 determines the classification of operation or the like on a basis of discrimination of the conditional branching instruction or the nonbranching instruction. The output of the circuit 6 is inputted to the circuit 7 and a memory addressing circuit 8. The circuit 8 determines a memory address to be next accessed in accordance with the conditional branching instruction or the nonbranching instruction. |
