| 摘要 |
PURPOSE:To derive easily an instruction fetch cycle by attaching a data for discriminating an address for showing the head and the terminal of each program of an object to be checked, to a memory map of a debugging device addressed in parallel to an actual machine. CONSTITUTION:A memory map 4 to be addressed in parallel to a memory 2 of an actual machine A is provided on a debugging device B, and an address corresponding to an address of the memory 2 is provided in the map 4. A prescribed data is inputted in advance through a multiplexer 5 from a CPU3, to an address of the memory map 4 corresponding to an address for showing the head and the terminal of each program in the memory 2 to be checked. When a program of the actual machine starts to run, the multiplexer 5 selects the memory 2, and simultaneously, the addressing is started, and when the address of the memory map attains a prescribed value, it is outputted, and a timing of a timing detecting circuit 6 is outputted from an AND circuit 7. In this way, an instruction fetch cycle is derived easily. |
