发明名称 MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
摘要 PURPOSE:To shorten and facilitate the wiring between variable length cells, by providing an arrangement improving process, by which the variable length cells are exchanged and arranged when the areas of the cells are different. CONSTITUTION:The areas of all variable length cells other than basic variable length cell are the integer times the area of the variable length cell. The variable length cell 3B has the area twice the basic variable length cell 3A. The variable length cell 3A and a variable length cell 3C in the vicinity thereof are combined so that the area becomes equal to the area of the variable cell 3B. The variable length cells 3A and 3B are exchanged and arranged. In this way, the restriction of the arranging pattern of the variable length cells can be eased, and the wiring between the variable length cells is shortened and facilitated.
申请公布号 JPS59132144(A) 申请公布日期 1984.07.30
申请号 JP19830005907 申请日期 1983.01.19
申请人 HITACHI SEISAKUSHO KK 发明人 YUYAMA YASUSHI;TAKECHI MAKOTO
分类号 H01L21/822;H01L21/82;H01L27/02;H01L27/04;H01L27/118 主分类号 H01L21/822
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