| 摘要 |
PURPOSE:To avoid a synchronizing signal clock from being expanded and compressed unstably by means of the synchronizing operation by extracting the level of phase jitter from the result of demodulating sampling, averaging a synchronizing error during a certain number of periods and comparing the average value and the level of phase jitter. CONSTITUTION:Suppose that an input is 32 sets of demodulating sampling values per period. A majority discriminating circuit 13 applies the principle of decision by majority to the result of demodulating sampling and discriminates input data. A flag detecting circuit 14 extracts the synchronizing error from the result of discrimination by the circuit 13 and a synchronizing error extracting circuit 15 adds the synchronizing error of the period just before and the result of extraction by the circuit 14 by taking 32 as a modulus. A phase jitter extracting circuit 16 extracts a phase jitter. A synchronizing error averaging circuit 17 takes arithmetic mean at adjacent periods having a data changing point of the synchronizing error. Further, a synchronizing circuit 18 discriminates whether the average synchronizing error is larger than the phase jitter or not, inputs a synchronizing clock ''1'' and attains synchronism by expanding and compressing the synchronizing clock of the average synchronizing error component. |
