发明名称 Load-limiting network for a power transistor
摘要 The power dissipation within the transistor (1) can be greatly reduced by simple means by using a capacitor (7) which acts in a voltage-delaying manner on a transistor (1) during the turn-off and by using a coil (5) which acts in a current-delaying manner on the transistor (1) during the turn-on. The released energy which is contained in the coil (5) during the turn-off can also be conducted via a load-limiting diode (6) back to an input driver stage (2) where it additionally acts in a power-saving manner when the transistor (1) is turned on. <IMAGE>
申请公布号 DE3247707(A1) 申请公布日期 1984.06.28
申请号 DE19823247707 申请日期 1982.12.23
申请人 BROWN,BOVERI & CIE AG 发明人 PETSCHENKA,EDWIN,DIPL.-ING.;BECKER,GERHARD
分类号 H03K17/00;H03K17/0814;(IPC1-7):H03K17/08;H02H7/20 主分类号 H03K17/00
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