| 摘要 |
PURPOSE:To improve an execution speed by using a storage means with (n)-bit length indicating the number of shifts and a bit shifter whose performance of 2<i>-bit shifting is determined according to the value of the (i)th bit of the shifter. CONSTITUTION:The register 1 is stored with binary information indicating the number of shifts by shift operation and has five-bit constitution including the least significant digit bit 2 and most significant digit bit 6 to express numbers 0-31. Bit shifters 7-11 are 1, 2, 4, 8, and 16 bit shifters are controlled through a control signal according to values of corresponding bits of the shift register 1. For example, when the value of the shift register 1 is 10101, data from a bus 12 is shifted by 16 bits through the shifter 11 and inputted to the shifter 10, wherein the data is not shifted; and the data is inputted to the shifter 9 for a four-bit shift, and supplied to the shifter 7 for a one-bit shift through the shifter 8. Thus, the data is shifted by 21 bits in totally and outputted from a bus 13. |
