| 摘要 |
PURPOSE:To use properly both a first-in/first-out memory and a last-in/first-out memory, by providing an address control circuit of hardware structure of a small amount and a timing signal generating circuit to a random access memory. CONSTITUTION:The addressing is carried out by an address control circuit 3. A switch circuit 9 delivers the output of an adder 8 as an address data. In the case of a first-in/first-out memory FIFO, a counter 7 is reset with a reset signal P3. At the same time, an up-down switch signal P2 is held at a count-up state. Then the address data is applied together with signals P1, P4 and P5 to read out data successively. In the case of a last-in/first-out memory LIFO, the counter 7 is held at the writing contents. Then the signal P2 is set in a count-down state to read the data. Both writing and reading are possible to set the circuit 9 at an address path 5. In such a way, both FIFO and LIFO memories can be used properly. |
