| 摘要 |
PURPOSE:To set an optimum transfer speed in accordance with a load of a common bus, by providing a register for determining to reset a counter when how many clocks are counted by the counter which counts the period of a data transfer request. CONSTITUTION:At the time of start, a processing device sets a tranfer speed to a data transfer speed register RG 38 of a direct memory access DMA memory device 3. In case when a data is written in a main storage device, the device 3 outputs a data and an address from an RG 36 and an RG 32, respectively, and when the storage device sets it, a data transfer completion signal 48 is outputted to a counter 41. Subsequently, a data whose MSB is ''0'' is set to the counter 41 from an RG 38, a clock 52 is inputted from a clock generating circuit 52 through an invertor 42 and an AND gate 40, and when the counter 41 is added with +1, and MSB goes to ''1'', AND 43 is executed by a signal 44 from the counter 41, a signal 46 from a data transfer word number storing RG 31, and an operation completion signal 45 from an IC memory 35, and a bus occupying signal 47 is outputted. |
