PROGRAMMABLE COUNTER CIRCUIT

摘要

In order to improve the operable frequency of a programmable counter circuit which serves as an N-step counter by loading an initial value N, load terminals of flip-flops of respective stages forming the counter circuit are sequentially cascade-connected via buffers and a load signal is applied to each of the load terminals from a load signal generator circuit. By a detector circuit is detected a specified value which is provided a little before the initial value loading of the counter circuit. The detected output is shifted by a shift register which operates on the same clock signal as that for driving the counter circuit, thereby to generate the load signal at the moment of the initial value loading of the counter circuit. In this case, for the duration of the load signal and a certain period of time subsequent thereto the application of the output from the detector circuit to the shift register is inhibited, thus preventing erroneous loading.