发明名称 VERIFICATION SYSTEM OF INFORMATION PROCESSOR
摘要 PURPOSE:To perform easy and secure verfication by accepting and processing an optional microprogram steal request at a program address. CONSTITUTION:When the microprogram of a basic processor is executed up to a prescribed address in a muP address register 2, a comparing circuit 9 obtains an address coincidence to generate an output signal 28 of ''1''. Therefore, an OR signal 31 is held at ''1'' to open an AND circuit 12, and a muP steal request signal SO inhibited so far is accepted by an execution order control circuit 1. Then, an address for processing the signal SO is generated by the circuit 1 and set in the register 2, thereby handling a corresponding microprogram steal request.
申请公布号 JPS5882341(A) 申请公布日期 1983.05.17
申请号 JP19810179677 申请日期 1981.11.11
申请人 HITACHI SEISAKUSHO KK 发明人 NOMOTO SHINSUKE
分类号 G06F9/22;G06F11/28;G06F11/36 主分类号 G06F9/22
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