发明名称 Circuit arrangement for monitoring a signal over time
摘要 In this arrangement, each frequency or amplitude deviation which lasts longer than a predetermined time interval (t1, t2) is to be indicated by an error signal. According to the invention, this is achieved by the fact that the circuit arrangement switches to a first or second switching state in dependence on the occurrence of such a deviation, via a comparator (4) which compares the signal (ue) to be monitored with a reference signal. In the first switching state, recharging processes occur between three capacitors (C1, C2, C3), by means of which processes the third capacitor (C3) is charged up step by step. If the deviation persists beyond the time interval, the third capacitor (C3) reaches a state of charging which leads to an error signal. If the deviation disappears within the time interval, the arrangement switches to the second switching state in which the capacitors become discharged. The field of application includes an FM modem of a videotex system. <IMAGE>
申请公布号 DE3134056(A1) 申请公布日期 1983.03.10
申请号 DE19813134056 申请日期 1981.08.28
申请人 SIEMENS AG 发明人 KNAUER,KARL,DR.
分类号 G01R19/00;G01R23/00;(IPC1-7):G01R19/16;G01R23/06;H04N1/00 主分类号 G01R19/00
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