发明名称 PSEUDO FAULT GENERATING CIRCUIT
摘要 PURPOSE:To check a retrying circuit accurately by providing a pseudo fault generating circuit with mechanism which clocks a prescribed time, and thus generating a pseudo fault signal for the prescribed time when the pseudo fault generating circuit is started. CONSTITUTION:Instructions are executed by an instruction executing circuit 1, whose execution results are checked by a checking circuit 2. If this circuit 2 detects an error, the execution of the instructions is retried under the control of a retry control circuit 4. At this time, a pseudo fault generating circuit 4 provided with a counter 4' generates and send a pseudo fault signal to the executing circuit 1 and checking circuit 2 for a prescribed time set in the counter 4'. Then, the checking circuit 2 sends an error signal to a control circuit 3 until the timer 3' reaches the prescribed time, and once no error is found, the control is returned to the normal conditions to eliminate overretrying, thus preventing the operation of the computer from being stopped.
申请公布号 JPS5839351(A) 申请公布日期 1983.03.08
申请号 JP19810136700 申请日期 1981.08.31
申请人 FUJITSU KK 发明人 IWATA KATSUYUKI
分类号 G06F11/22 主分类号 G06F11/22
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