Semiconductor memory test equipment

摘要

A semiconductor memory test equipment which reads out a memory under test by an address from a pattern generator and compares the read-out data with an expected value by a comparator, and in which a block mask memory is read out by a portion of the address and the comparing operation of the comparator is inhibited by block mask data read out from the block mask memory. Pattern data for a pattern memory, which is read out by the abovesaid address to store data to be supplied to the comparator, are transferred as parallel data from a central processor and written in the pattern memory after conversion to serial data, and serial data read out from a defective address memory are inputted to the central processor after conversion to parallel data.