VIDEO SIGNAL PROCESSOR

摘要

A phase control circuit (5) sets the phase of a sampling clock signal for A/D conversion of a video signal in order. A binarizing circuit (6) binarizes an analog video signal. A first counter circuit (7) counts the changes of the output signal of the binarizing circuit (6). An A/D converting circuit (2) digitizes the input signal. A second counter circuit (8) counts the changes of the most significant bit of the A/D converting circuit (2). A subtracting circuit (9) subtracts one from the other of the output signals of the two counter circuits. By changing the phase of the sampling clock signal of the A/D conversion in order within one period, the subtraction results are found, and this process is repeated for one or more periods. Thus the phase of the optimum sampling clok is set according to the subtraction results.