| 摘要 |
PURPOSE:To detect an error by which a mistake is given to the full bit logic ''0'' or ''1'', by performing an odd parity check based on the clock signal which is produced prior to the transfer of data and then carrying out an even parity check based on the following clock signal. CONSTITUTION:The signals corresponding to logic ''0'' and ''1'' are stored in the parity set bit storing parts 3 and 14 respectively based on the clock signal CL which is used for the transfer of data DATA0-DATA7. For instance, when the logic ''0'' is stored in the parts 3 and 14 each, the logic ''1'' is delivered for the parity bit in a parity producing circuit 11 and to ''10110100'' of the DATA0- DATA7. A parity checking circuit 12 checks the data including a parity bit PB plus the logic ''0'' of the part 14 in the form of a piece of data. After this, the next clock signal CL is applied to the parts 3 and 14 respectively. As a result, the logic ''1'' is stored in the parts 3 and 14 each. |
