发明名称 ENDORESUTEEPUNOKIROKUSAISEISOCHI
摘要 <p>PURPOSE:To increase the range of application of an endless tape, by setting the reference point of recording and reproduction while the time required for a round of the endless tape is divided into sections. CONSTITUTION:A PLL circuit consists of a phase comparator 14, a clock oscillator 16 and a counter part 17; and the divided signals are produced just once from a counter 17 synchronously with the reference signal while the reference signal is detected, i.e., an endless tape 11 runs a round. For instance, if a counter 17 functions as a 1/N dividing circuit, the frequency of oscillation of the oscillator 16 is controlled while the tape 11 has a round. Accordingly under such conditions, the counter 17 is advanced at the time points when the time required for a round of the tape 11 is devided equally into N sections, and the count value shows the range of division of the tape position corresponding to a recording/reproduction head for example. In other words, the count value of the counter 17 receives a comparison 19, and a coincidence EQ is detected. Thus the detection output of the dividing positions can be obtained for the desired tape 11.</p>
申请公布号 JPS5753863(A) 申请公布日期 1982.03.31
申请号 JP19800126743 申请日期 1980.09.12
申请人 TOKYO SHIBAURA ELECTRIC CO 发明人 KATSUBE FUJIO
分类号 G11B15/02;G11B15/70 主分类号 G11B15/02
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