发明名称 OUTPUT COLLATION SYSTEM FOR DIGITAL CONTROLLER
摘要 PURPOSE:To prevent misoutput, by constituting an output pulse from the time when a redundant pulse outputted asynchronizingly is present to the time when it is absent. CONSTITUTION:An input data A is fetched to operation sections 2, 3 via a data input section 1. Processed output data B and C are transmitted to data latch circuits 8 and 9. This output is transmitted to an output latch circuit 10 via an AND circuit 9, and an output is started at the time when both the outputs are incoincidence. Both the outputs are applied to an NOT circuit 12 via an OR circuit 11, and the latch circuit 10 is reset when both the outputs are turned off. Thus, the output signal D has the same pulse width as the output data B and C, allowing to prevent the effect due to shift in output timing.
申请公布号 JPS5752902(A) 申请公布日期 1982.03.29
申请号 JP19800125950 申请日期 1980.09.12
申请人 HITACHI SEISAKUSHO KK 发明人 KANZAKI HIDEO;MIZOGUCHI TSUYOSHI;AOTSU HIROAKI
分类号 G05B9/03;G06F11/18 主分类号 G05B9/03
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