发明名称 FAULT DETECTION SYSTEM
摘要 PURPOSE:To detect faults in the system rapidly and efficiently by a monitor device, by causing respective devices to be monitored to report faults of themselves to the monitor device spontaneously. CONSTITUTION:When power break occurs in a node ND 3, clock break is detected by a receiver 1 in the LA 4 side in an ND 4, and its information is reported to an input/output signal control part 7, and a corresponding pattern is generated there and is written in both buffer memories 3 and 4 in the LA side and the LB side. The contents of buffer memories 3 and 4 in the LA side and the LB side are read out by various transmission clocks and are transmitted to respective transmission lines of the LA 5 and the LB 4 by transmitters 5 and 6. In an ND 2, a bit pattern corresponding to detected clock break of the receiver in the LB 3 side is transmitted to the LA 3 and LB 2 similarly. A monitor device SV detects that communication with the ND 3 is impossible on a basis of information of clock break of the LA line of the ND 4 received from the LA line and clock break of the LB line of the ND 2 received from the LB line.
申请公布号 JPS573153(A) 申请公布日期 1982.01.08
申请号 JP19800076173 申请日期 1980.06.06
申请人 FUJITSU LTD 发明人 HAYASHI NARUHIRO;MORIKAWA HISASHI
分类号 G06F11/30;G06F11/00 主分类号 G06F11/30
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