发明名称 |
PHASE LOCKED LOOP TYPE FREQUENCY SYNTHESIZER |
摘要 |
In a phase lock loop frequency synthesizer, a successive addition rate multiplier provides a correction signal for eliminating ripple in a frequency control signal applied to a variable frequency oscillator which produces the output frequency of the synthesizer. Ripple elimination is improved by means of a feedback loop by which any residual ripple is detected and the correction signal is automatically adjusted. |
申请公布号 |
JPS56110345(A) |
申请公布日期 |
1981.09.01 |
申请号 |
JP19810006578 |
申请日期 |
1981.01.21 |
申请人 |
PHILIPS NV |
发明人 |
NIIJIERU JIYON UORUTAAZU;MIIKERU JIEEMUSU ANDAAHIRU |
分类号 |
H03L7/18;H03L7/081;H03L7/187;H03L7/197 |
主分类号 |
H03L7/18 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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