发明名称 SEMICONDUCTOR MEMORY DEVICE
摘要 PURPOSE:To obtain high detection sensitivity by a method wherein the memory device is constructed by FET of which conductance varies according to existance of an electric charge between a source and a drain and a dummy cell having an almost same structure as that of FET but being 1/2 of FET in the ratio of length to width of a channel. CONSTITUTION:P<+> type regions 16 surrounding a channel region are diffusion- formed on the periphery of a P type Si substrate 13, and a thin film oxide 11 tapered in a direction of the channel region is cover-attached on the regions 16. Then, a deep N type region 14 and a shallow P type region 15 are layer-built and diffusion- formed in the channel region surrounded by those regions 16, and a polycrystalline Si gate electrode 12 is cover-attached on the region 15, extended to the ends of the film 11 through a thin gate film oxide. Thereafter, the thus constructed memory cell 21 is connected to the dummy cell 23 through a sense amplifier 22. In this case, the ratio of the length to the width of the channel of the cell 23 is chosen to approximately 1/2 of the cell 21, and the ratio of the conductance is taken as 1:2. The detection sensitivity of the cell is thus improved.
申请公布号 JPS56105665(A) 申请公布日期 1981.08.22
申请号 JP19800007525 申请日期 1980.01.25
申请人 TOKYO SHIBAURA ELECTRIC CO 发明人 MASUOKA FUJIO
分类号 G11C11/412;G11C11/4099;H01L21/8242;H01L27/108;H01L29/78 主分类号 G11C11/412
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