| 摘要 |
<p>An output buffer circuit operable at a high-speed and stably holding output level is disclosed. The output buffer circuit comprises a pair of input transistors receivivable a true and a complementary signals, a pair of output nodes from which amplified signals of the true and complementary signals are derived. a pair of switching gates coupled between the drains of the input transistors and the output nodes and control means for operatively disenabling the switching gates when logic state of the true and complementary signals applied to the input transistors is reversed.</p> |
