| 摘要 |
Digital phase-locked loop, preferably for bit rate regeneration in synchronous data transmission systems, transmitting from a sender to a receiver redundantly coded information possibly modulated in a suitable mode. An addition circuit (6) is connected to one control input of the digital controlled oscillator (4) incorporated in the loop, said addition circuit adding control signal contributions from the phase comparator circuit (5) of the loop and an error detector (3). This error detector (3) is connected to the output of the receiver data detector, and examines whether the input signal in the circuit has the expected inherent redundant properties expected taking into account the signal coding. When this is not the case, a pulse-shaped control signal is fed to the addition circuit (6). |
