| 摘要 |
PURPOSE:To shorten a decoding processing time by composing a circuit for the polynominal calculation of the number of error locations and error-bit-position calculation of a conversion table between vector expression codes of elements in a Galois field and powers, adder-subtracter circuit and register. CONSTITUTION:To decode a two-element BCH code, syndrome Sj is calculated by received code polynominal expression r(X). Syndrome Sj is inputted to the calculation circuit for coefficient (sigmaj) of the polynominal expression of error location composed of registers REG1 to REG7, adder circuit ADD, and exclusive-OR circuit EXOR. This circuit is provided with both-way conversion tables TB1 and TB2 between vector expression code (a<k>) of element (a) in the Galois field and power (k), and multiplication is substituted by addition. Similarly, coefficient (sigmaj) is inputted to the error-bit-position calculation circuit consisting of registers REG8 to REG11, ADD, EXOR, and conversion tables TB1 and TB2; error bit position (k) is calculated and after it is discriminated by decision circuit CHK, the code error of a received-code sequence r(X) stored in REG11 is corrected, thereby outputting decoding output s(X). |
