Non-committed logic cell array - with each cell contg. symmetrical transistor pattern, transistors having electrode regions connected to externally accessible contact areas

摘要

The uncommitted logic array has logic cells each of which comprises a symmetrical array of transistors. Four pairs of complemetanry IGFET s (6A-D, 8A-D) are arranged concentrically. The gate electrodes of each pair of transistors are connected to a common electrode (24A-D). The outer transistor of each pair has individual source and drain terminals while the inner transistors have source and drain terminals (32A-D, 30A-D) one of which (32A-D) is individual to the device whereas the other is shared with the internal resistor of the adjacent pair. A central power terminal (34) two earth terminals (36, 38) and peripheral buried connections (64) are provided. A customised metallisation layer commits the array to a desired logic function. The layout of the cells provides good packing density whilst enabling easy interconnection.