发明名称 MANUFACTURE OF SEMICONDUCTOR DEVICE
摘要 PURPOSE:To shorten the process, and improve the controllability of gate length by a method wherein, after an insulating film is formed, a gate is patterned with photoresist, metal is vapor-deposited, the resist is eliminated, and then the insulating film is subjected to anisotropic etching. CONSTITUTION:A gate is patterned on an insulating film 3 with photoresist PR1, and metal 2 is vapor-deposited on the PR1 and the film 3; an aperture pattern is formed with metal having a specified gate length; a gate aperture is formed by anisotropic etching of the film 3. Althrough the PR patterning is restricted by the resolution of an aligner, a gate pattern whose gate length is finer than the resolution dimension is obtained by lengthening the developing period, because the PR dimension left as a gate pattern depends on the developing period. Thereby, two times growth of insulating film is made one time growth for process reduction, and the controllability of the gate length is improved.
申请公布号 JPH023923(A) 申请公布日期 1990.01.09
申请号 JP19880152635 申请日期 1988.06.21
申请人 NEC CORP 发明人 URABE JUNICHI
分类号 G03F1/00;H01L21/28;H01L21/302;H01L21/306;H01L21/3065;H01L21/338;H01L29/80;H01L29/812 主分类号 G03F1/00
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