DATENAUSTAUSCHSTEUERUNG FUER ZWEI MIKROCOMPUTER

摘要

A data exchange control in full-duplex mode is proposed for two microcomputers (MR1, MR2) which in each case essentially consist of a microprocessor (CPU1, CPU2) controlled by a clock generator (TG1, TG2). The data bus is connected to a system memory (SSR1, SSR2) for programs and data and input and output units which are activated by addresses conducted via an address bus and separate control signals. For this purpose, each microcomputer is equipped with a FIFO (first-in-first-out) memory which, with the aid of program-controlled signals, allows the required data exchange during a data transmission between the two microcomputers in the transparent mode in block traffic to be decoupled in time. The transmitted data words are not themselves used for controlling the transmission. <IMAGE>