High speed binary and binary coded decimal adder

摘要

A high speed binary and binary coded decimal adder which employs a plurality of partial adders and a carry look ahead circuit and is adapted to effect a binary coded decimal addition with only one processing of the adder. The partial adders are each composed of a half adder for generating a bit generate signal and a bit propagate signal, a binary mode carry look ahead input signal generator circuit part, a binary coded decimal mode carry look ahead input signal generator circuit part, an intermediate adder part and a full adder part. The high speed binary and binary coded decimal adder is capable of providing the result of an addition at a speed corresponding to six to seven logical stages.