| 摘要 |
PROBLEM TO BE SOLVED: To control the duty of an output pulse to a desired value independently of a clock waveform of a synchronous circuit such as a shift register. SOLUTION: A clock frequency divider circuit (DIV) 110 outputs a signal MPR resulting from applying 1/2 frequency division to a clock signal CLK to a programmable delay line (DL-MTX) 140. A counter circuit (CNT) 120 counts a reference delay stage number DREF equivalent to one period of the clock, a duty adjustment circuit (DUTY-ADJ) 130 calculates a delay setting stage number DREFH on the basis of the reference delay stage number DREF and outputs it to the programmable delay line (DL-MTX) 140. The programmable delay line (DL-MTX) 140 generates a delay signal DMPR resulting from delaying the clock frequency division signal MPR on the basis of the delay setting stage number DREFH and generates a delay signal ZMRP resulting from delaying the clock frequency division signal MPR0 stage. A pulse train generating circuit (MP-GEN) 150 calculates an exclusive OR between the delay signals DMPR and ZMPR and provides an output of a pulse train MP. |
