发明名称 |
Small duty cycle current limiter - has logic circuit delaying start signal for next cycle according to load current integral valve |
摘要 |
<p>A current limiting circuit using an intermittent operating method with small duty cycle, in partic. an impulse operating method with phase control, is designed so that the time interval between successive pulse groups is large w.r.t. the duration of the pulse groups. In each operating cycle the current in the load is integrated and compared with a defined max. value. The current-time integral is retained after the on cycle. A logic circuit is used to delay the start signal for the next on cycle according to the integral value. After the comparator detects an integral greater than the threshold level the start signal delay is regenerated from one interval to the next in steps.</p> |
申请公布号 |
DE2605500(A1) |
申请公布日期 |
1977.08.18 |
申请号 |
DE19762605500 |
申请日期 |
1976.02.12 |
申请人 |
GIESENHAGEN KG |
发明人 |
WALTER,DIETER,DIPL.-PHYS.;HAMACHER,HANS |
分类号 |
G05F1/455;(IPC1-7):G05F1/40 |
主分类号 |
G05F1/455 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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