EEPROM with NAND memory cells - has potential stabiliser above semiconductor support layer, next to respective data transmission line

摘要

The memory has a semiconductor support layer (12), parallel data transmission lines (BL) on top of the layer, and a memory cell section with an array of programmable memory cells (M1-8), associated to given bit line (16, BLi) of the data transmission lines. A potential stabiliser (72) is insulatingly fitted above the support layer, adjacent to the above mentioned bit line. It receives a preset constant voltage applied to the support layer during a selected time period, during which data access takes place in a cell unit of NAND type. The cells of the NAND unit (14i) have a series connection of a preset number of data storage transistors with control gate layers, and a switching transistor (QS1). ADVANTAGE - High integration and improved operational reliability.