| 摘要 |
<p>PURPOSE:To obtain a semiconductor memory in which reading speed is increased. CONSTITUTION:Memory cells C00, C01 of two rows and four stage are provided between two lines BS0, BS1. In a pre-charge period, the lines BS0, BS1 are previously charged to Vcc by transistors for pre-charge QPR0, QPR1. In a discharge period, even if transistors for discharge Qpc0, QDC1 both are made an ON state, since only either of transistors Qs0, Qs1 is made an ON state, only either of the lines BS0, BS1 is discharged first. For example, when a selection memory cell is placed at a left side block BLKO (AR0=0), the transistors Qs1, QDC1 are made a ON state, the line BS1 is discharged first, and the line BS0 is discharged in accordance with data of the selection memory cell.</p> |
