| 摘要 |
PROBLEM TO BE SOLVED: To shorten a development period of a semiconductor integrated circuit. SOLUTION: A design layout creation method of a semiconductor integrated circuit is provided with a step (ST1) for extracting the combination of a plurality of cells constituting a circuit pattern where an OPC dangerous place is generated when those cells are adjacently arranged, and for constraining the arrangement of cells; a step (ST2) for arranging the plurality of cells; a step (ST3) for extracting the OPC dangerous place in the combination of the plurality of adjacently arranged cells on the basis of the arrangement constraint; a step (ST4) for performing flipping processing on the same coordinates to at least one cell in the combination of the cells including the OPC dangerous place to change a layout; and a step (ST6) for performing the decomposition processing or composition processing of the cells to the combination of the cells including the OPC dangerous place which has not been removed in the flipping processing to change the layout. COPYRIGHT: (C)2009,JPO&INPIT
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