| 摘要 |
PURPOSE:To enable varied controls for tests to achieve an inspection in a short time, by creating a test-ready state different from that when an input is applied to a testing input terminal in the normal operation, where an input is applied to the testing input terminal while the combination of logical states in the inputting of a key will not exist as such under the predetermined combination. CONSTITUTION:In the normal operation, when a 7-input AND circuit detects that an input T is applied to a testing input terminal under the condition to meet the Boolean expression indicating the combination of logical states which will not exists when any of keys is depressed or a plurality of keys are depressed in multiplication, it is latched with an R-S flip flop 1 to generate a signal TM indicating a test-ready state to create a test-ready state different from that when an input is applied to the testing input terminal in the normal operation. |
